1. Field of the Invention
The invention relates to a wiring configuration for memory module, for example, a Single (SIMM) or Dual In-Line Memory Module (DIMM).
2. Description of the Related Art
Memory Modules (e.g. Single In Line Memory Modules (SIMMs), Dual In Line Memory Modules (DIMMs), etc.) are an essential part of almost every computer. In fact, the random access memory (RAM) of most computers is comprised mainly of memory modules. Computer mother boards often include expansion ports for the placement of additional memory modules to increase the memory capacity of the computer. The memory module is essentially a circuit board with memory devices affixed to one or both sides thereof. These memory devices are typically DRAMs, but may also comprise other similar memories (e.g., SDRAMs, SRAMS, etc.) The circuit board also include terminals, or "pins" which facilitate communications between the memory devices and the rest of the computer (e.g., CPU, etc.). In Line Memory Modules (IMMs) are the most popular memory modules for use in computer systems. They include SIMMs and DIMMs. For convenience the ensuing discussion describes IMMs as representative of memory modules with which the invention may be used.
Most IMMs on the market today include an Electrically Erasable Programmable Read Only Memory (EEPROM) containng configuration information relating to the IMM. One of the main functions the EEPROM performs is serial presence detect (SPD) commonly used in computer systems. SPD is a method by which a IMM identifies itself to a (CPU of a computer through information stored in the EEPROM. The SPD is performed by a SPD processor in conjunction with the EEPROMs of the IMMs. When the computer first boots up, the SPD controller reads out the EEPROM of each memory module in order to identity to the CPU how much and what type of memory is installed.
FIG. 1 shows an exemplary IMM with an associated EEPROM attached thereto. The EEPROM typically includes 256 bytes of storage capacity. The first 128 bytes are used to store industry standard information relating to the IMM. The contents of each of these 128 bytes is specified by the Joint Electron Device Engineering Council (JEDEC). The other 128 bytes are usually reserved for use by either the manufacturer or purchaser of the IMM. Using a conventional JEDEC protocol, the EEPROMs of only eight IMMs can be addressed by the SPD controller because of the limited number of address pins (3) on the EEPROM and the computer bus structure. This causes a problem because it limits the amount of memory that can be utilized by the computer.
Recently, a new type of memory module architecture has been developed which allows more than eight memory modules and their associated EEPROMs to be addressed by a CPU. This new module is referred to as a "daisy chain" module because it has the capability to link together with other memory modules to increase memory capacity of a computer. The "daisy chain" memory module contains an EEPROM which is different from the EEPROM of the JEDEC specification and includes pins not present on traditional EEPROMs, which provide ports for the clock signals of several EEPROMs to be serially interconnected. By linking together the multiple EEPROMs of the multiple memory modules, the number of memory modules which can be addressed becomes unlimited. This new memory architecture is beginning to gain popularity and is being deployed in IMMs.
Since most IMMs were developed with configurations for the JEDEC standard only at present a memory module manufacturer must stock different circuit boards for JEDEC type of memory module and associated EEPROM as well as for a "daisy chain" type of memory module and its associated EEPROM. There is accordingly a current need for an IMM mounting board which can support either the JEDEC standard EEPROM or the newer "daisy chain" EEPROM, yet be universally accepted by computer systems designed for use with either architecture. There is also currently a need for a method for transforming exisitng circuit boards so that they can be used with either the JEDEC standard or the "daisy chain" EEPROM.